1. Field of the Invention
The present invention is generally related to the field of semiconductor manufacturing and, more particularly, to plasma state monitoring to control etching processes and across-wafer uniformity, and a system for performing same.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
As device dimensions have continued to decrease, the ability to precisely form very small features to their desired dimension has become more important. Variations in the physical dimensions of such features can adversely impact device performance and reduce product yields. For example, the critical dimension and profile of gate electrode structures of transistors is one area where a very high degree of precision is desired. Absent precise control, adverse consequences may follow. For example, if the critical dimension of the gate electrode is greater than the target or design critical dimension, the transistor may not operate as fast as desired by the product design requirements. Conversely, if the critical dimension of the gate electrode structure is less than the target value, off-state leakage currents may be higher than desired. This situation is particularly problematic for integrated circuit devices intended for mobile telecommunication applications and those intended for mobile computing devices.
Etching processes are frequently employed in semiconductor manufacturing to define a variety of different types of features, such as gate electrode structures, conductive metal lines, openings in insulating layers, trenches in a semiconducting substrate, sidewall spacers, etc. Such etching processes, be they anisotropic or isotropic in nature, are very complex processes that involve a vast variety of interrelated variables, such as gas flow rates, temperature, pressure, power, etc. Such complexities make it difficult to control etching processes such that the resulting features exhibit the desired physical dimensions and/or profile.
Moreover, in some cases, wafers exhibiting across-wafer irregularities are sent to an etch tool for processing. For example, a deposited layer of material may be thicker near an edge region of the wafer and relatively thinner near the central region of the wafer. This thickness variation may be due to a variety of factors. In that case, performing a standard etch process that is based upon the premise that the process layer on the incoming wafer exhibits substantially uniform across-wafer thickness characteristics may lead to severe process errors. For example, if a deposited layer is thicker near the edge of the wafer, an endpoint etch process may be performed for too long of a duration, thereby overetching the deposited area in the middle region of the wafer. Such overetching may cause undesirable damage to the underlying process layer or increase the likelihood that features formed in the deposited layer may exhibit less than desired profiles. As a result, the devices produced by such processes may produce completed integrated circuit devices of an unacceptable quality.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.